10/7隨堂練習

題目:Design a verilog model of a adder and write a testbench to verify the designed verilog model

module Add_half(sum,c_out,a,b);

input a,b;

output sum,c_out;

wire c_out_bar;

xor(sum,a,b);

nand(c_out_bar,a,b);

not(c_out,c_out_bar);

endmodule

module test;

reg a,b;

wire sum,c_out;

Add_half U0 (sum,c_out,a,b);

initial

begin

a = 0; b=0;

#10 a =0; b = 1;

#10 a =1; b = 0;

#10 a =1; b = 1;

#10 $finish;

end

endmodule