12/8 Verilog Behaviornl Model

module D_filp_flop ( q , data_in , dk )
input data_in , clk;
output q;
reg q;

always@( clk )
begin
if ( clk == 0 )
q = q;
else
q = data_in;
end
endmodule

11/24 加分

module aaa;

wire a,b,c,d;

wire c_out;

system_clock #800 clock(a);

system_clock #400 clock(b);

system_clock #200 clock(c);

system_clock #100 clock(d);

xxx t(c_out,a,b,c,d);

endmodule

module xxx(c_out,a,b,c,d);

input a,b,c,d;

output c_out;

wire w1,w2,w3,w4,w5,w6,a_bar,b_bar,c_bar,d_bar;

not(a_bar,a);

not(b_bar,b);

not(c_bar,c);

not(d_bar,d);

and(w1,a_bar,b_bar,c_bar,d);

and(w2,a,b,d);

and(w3,b,c,d);

and(w4,a,c,d);

and(w5,a_bar,c,d_bar);

and(w6,a,b_bar,c);

or(c_out,w1,w2,w3,w4,w5,w6);

endmodule

module system_clock(clk);

parameter PERIOD=100;

output clk;

reg clk;

initialclk=0;

always

begin

#(PERIOD/2) clk=~clk;

#(PERIOD/2) clk=~clk;

end

always@(posedge clk)

if($time>1000)#(PERIOD-1)$stop;

endmodule

時脈

module system_clock(clk);
parameter PERIOD=100;
output clk;reg clk; //reg可以用在像C語言的用途
initialclk=0; //clk初始值設為0
always
begin
#(PERIOD/2) clk=~clk;
#(PERIOD/2) clk=~clk;
end
always@(posedge clk)
if($time>1000)#(PERIOD-1)$stop;
endmodule

11/17 2-bit比較器

module Compare_2_str( A_lt_B , A_gt_B , A_eg_B , A0 , A1 , B0 , B1 );
input A0 , A1 , B0 , B1;
output A_lt_B , A_gt_B , A_eg_B;
wire w1 ,w2 , w3 , w4 , w5 , w6 , w7;

or ( A_lt_B , w1 , w2 , w3 );
nor ( A_lt_B , A_gt_B , A_eg_B );
and ( A_eg_B , w4 , w5 );
and ( w1 , w6 , B1 );
and ( w2 , w6 , w7 , B0);
and ( w3 , w7 , B1 , B0 );
not ( w6 , A1 );
not ( w7 , A0 );
xnor ( w4 , A1 , B1 );
xnor ( w5 , A0 , B0 );
endmodule

11/10

1.行為模式
always @(a or b)
c = a ^ b;

2.結構模式
and x1( c_out , a ,b);
xor x2( sum , a , b);

10/20 行為模式

module AOI_4_Unit( y_out , x_in1 , x_in2 , x_in3 , x_in4 );
input x_in1 , x_in2 , x_in3 , x_in4;
output y_out;
reg y1 , y2 , y_out; (與結構模式的不同處)
always
begin
#1 y1 = x_in1 & x_in2;
#1 y2 = x_in3 & x_in4;
#1 y_out = y1 ^ y2;
end
endmodule

10/20 結構模式

module AOI_4_Unit( y_out , x_in1 , x_in2 , x_in3 , x_in4 );
input x_in1 , x_in2 , x_in3 , x_in4;
output y_out;
wire y1 , y2;

and #1( y1 , x_in1 , x_in2 );
and #1(y2 , x_in3 , x_in4 );
nor #1( y_out , y1 , y2 );

endmodule