11/24 加分

module aaa;

wire a,b,c,d;

wire c_out;

system_clock #800 clock(a);

system_clock #400 clock(b);

system_clock #200 clock(c);

system_clock #100 clock(d);

xxx t(c_out,a,b,c,d);

endmodule

module xxx(c_out,a,b,c,d);

input a,b,c,d;

output c_out;

wire w1,w2,w3,w4,w5,w6,a_bar,b_bar,c_bar,d_bar;

not(a_bar,a);

not(b_bar,b);

not(c_bar,c);

not(d_bar,d);

and(w1,a_bar,b_bar,c_bar,d);

and(w2,a,b,d);

and(w3,b,c,d);

and(w4,a,c,d);

and(w5,a_bar,c,d_bar);

and(w6,a,b_bar,c);

or(c_out,w1,w2,w3,w4,w5,w6);

endmodule

module system_clock(clk);

parameter PERIOD=100;

output clk;

reg clk;

initialclk=0;

always

begin

#(PERIOD/2) clk=~clk;

#(PERIOD/2) clk=~clk;

end

always@(posedge clk)

if($time>1000)#(PERIOD-1)$stop;

endmodule